`timescale 1ns/1ps
`include "code/source/P5/ask_dem.v"

module test_dem_ask;

    // Generate clock
    reg clk;
    initial clk = 0;
    always #1 clk = ~clk;
    
    // Input registers
    reg [11:0] in;
    reg reset, in_valid;
    
    // Output wires
    wire write;
    wire dout;
    // Tasks
    reg decode_start = 0;
    localparam WAVE_LENGTH = 19999;
    reg [11:0] wave [0:WAVE_LENGTH];
    integer i = 0;
    
    initial begin
        $dumpfile("./release/test_dem_ask.vcd");
        $dumpvars(0, test_dem_ask); 
    end
        
    initial begin
        // 相对于 sim 文件夹的目录
        $readmemb("D:/programming/verilog/Digital_Communication_SelfTest/code/test/P5/code_wave_ask.txt", wave);
        reset = 1;
        in = 0;
        in_valid = 0;
        @(negedge clk);
        reset = 0;

        repeat(2) @(posedge  clk);
        @(negedge clk) in_valid = 1;

        for (i = 1230; i > 0; i = i - 1) begin
        @(posedge clk);
        end

        decode_start = 1;

        for (i = 0; i < WAVE_LENGTH; i = i + 1) begin
        in = wave[i];
        @(negedge clk);
        end

        in_valid = 0;

        repeat(10) @(posedge clk);
        // Exit the simulation
        $finish;
    end

    always@(negedge clk) begin
        if (write && decode_start) begin
        $display(dout);
        end
    end

    // Device under test (our adder)
    ask_dem dut (.rst_n(~reset), .clk(clk), .write(write), .dout(dout), .in(in), .in_valid(in_valid));

endmodule
